RISC-V SoC Tape-Out
Chip Design RISC-V Cadence
Hardware redaction techniques applied to RISC-V SoC in Cadence (TSMC180)
Works
Here are some of my recent projects. I'm always working on something new, so check back often!
MRAM Characterization
FPGA SystemVerilog MRAM
FPGA-based testing framework with XOR methodology and Hamming distance analysis
Polymorphic Gate FIR Filter
FPGA AMD Kria Polymorphic
Runtime-reconfigurable FIR filter on AMD Kria KV260 demonstrating polymorphic computing
RevEx — VR/AR Controller
Embedded C PCB Design Sensor Fusion
Non-optical wearable controller with haptic feedback and sensor fusion
MTJ Array Fabrication
Nanofabrication E-Beam Lithography MRAM
Magnetic Tunnel Junction arrays for MRAM and probabilistic computing research
Satellite Ground Station
REST API Yamcs Satellite
REST API improvements for cube satellite ground station using Yamcs